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page 1 of 29 features ? tpo true power on functionality ? increased btpo range ? mono-cell chopped hall system ? tim twisted independent mounting ? dynamic self-calibrating algorithm ? end-of-line programm able switching points ? tc of back-bias magnet programmable ? high sensitivity and hi gh stability of the magnetic switching points ? high resistance to mechanical stress ? digital output signal (voltage interface) ? short-circuit protection ? module style package with two 4. 7/47 nf integrated capacitors ? package: pg-sso-3-91 with nickel plating type marking ordering code package tle4983c-htn e6747 83acs3 sp0003-74272 pg-sso-3-91 general information: the tle4983c is an active hall sensor i deally suited for camshaft applications. its basic function is to map either a toot h or a notch into a unique elec trical output state. it has an electrical trimming option for post-fabrication trimming in order to achieve true power on capability even in the case of production spreads such as different magnetic configurations or misalignment. an additi onal self-calibration module has been implemented to achieve optimum accuracy dur ing normal running operation. it comes in a three-pin package for the supply voltage and an open drain output. programmable true power on sensor tle4983c-htn e6747 data sheet version 1.1 pg-sso-3-91
page 2 of 29 pin configurat ion pg-sso-3-91 pin definition and function functional description: the basic operation of the tle 4983c is to map a ?high posit ive? magnetic field (tooth) into a ?low? electrical output signal and to m ap a ?low positive? magnetic field (notch) into a ?high? electrical output. optionally th e other output polarity can be chosen by programming the prom. a magnetic field is considered as posit ive if the north pole of a magnet shows towards the rear side of the ic housing. since it seems that also backbias-reduced magnetic configur ations still show signific ant flux densities in one distinct direction the circuit will be optimised fo r one flux direction in order to provide an optimal signal to noise behaviour. for understanding the operation of the tle4983c three different modes have to be considered: initial operation after power up: this mode will be referred to as ?initial mode?. operation following t he initialisation before havi ng full information about the target wheel: this mode will be referred to as ?precalibrated mode?. normal operation with running target wheel: this mode will be referred to as ?calibrated mode?. pin no. symbol function 1 v s supply voltage 2 gnd ground 3 q open drain output
page 3 of 29 initial mode: the magnetic information is derived from a chopped hall amplif ier. the threshold information comes from a prom-register that may be programmed at any time, but only once (no eeprom). the magn etic information is compared against the threshold and the output state is set correspondingly. some h ysteresis is introduced in order to avoid false switching due to noise. in case that there is no prom-value available (prom has not been programmed before) the chip starts an auto-search for the actual magnetic value (sar-mode). the initial threshold value is set to this magnetic value. this feature can be used to find a tpo-value for providing correct programming in formation to the chip simply by setting the chip in front of a well-def ined static target. in this ca se a moving target wheel is not necessary. in case there is a prom value available, the open drain output wil l be turned on or off by comparing the magnetic field a gainst the pre-programmed value. during rotation of the target wheel a self -calibration procedure is started in the background. the ic memorises magnetic fiel d values for adjusting the threshold to an optimum value. the exact way of threshold adj ustment is described in more detail in the precalibrated mode. precalibrated mode: in the precalibrated mode the ic permanently m onitors the magnetic signal. to say it in more detail, it searches for minimum (caused by a notch) and maximum (caused by a tooth) values in the signal. once the ic has found a pair of min / max values it calculates the optimum threshold level and adjusts the system offset in such a way, that the switching occurs on this level. the intern al offset update algorithm checks also the magnetical edge in that point in time when an offset update is to be released. positive updates of the offset are released only at m agnetic rising edges, negative offset updates only on magnetic falling edges. otherwise an update on the wr ong magnetic edge may cause additional switching. the threshold adju stment is limited to increments of approx. 15mt per calibration in order to avoid tota lly wrong information caused by large signal disturbances (emc-events or similar). the optimum threshold level may differ depending on the target wheel. for example, for regular gearwheels the magnetic signal is close to a sinusoid and the optimum threshold value c an be considered as 50% value, which is the mean value between minimum and maxi mum signal. for camshaft wheels an optimum threshold may be at a different per cent-value in order to have minimum phase error over airgap variations. see fig.4 for def inition of this dynamic switching level. in case that the initial prom-value does not lead to a switching of the ic because it is slightly out of the signal rang e the ic nevertheless does its sw itch value correction in the background. after having corrected for a suffici ent amount the ic will start its output switching. the output switch ing includes some hysteresis in order to avoid false switching. during 16 switching events updates (number of updates depend on the magnetic signal) with 15mt are allowed.
page 4 of 29 every valid 1 minimum or maximum will be considered. after the next 16 switching events a single update of max. 15mt (in both directions) is allowed. for this single update the highest maximum and lowest minimum is taken into consideration. if the ic has not been programmed yet, it uses the default 50% value between the minimum and the maximum as switching level. 1 valid means signal detection with dnc
page 5 of 29 calibrated mode: after a certain number of switching events ( 32) the accuracy is considered to be quite high. at this time the chip is switched into an averaging mode (= calibrated mode) where only minor threshold corrections are allowed. in this mode a period of 32 switching events is taken to find the absolute minimu m and maximum within this period. threshold calculation is done with these minimum and maximum. a filter algorithm is implemented, which ensures that the threshold will only be updated, if t he adjustment value calculated shows in the same direction over the la st four consecutive periods. every new calculated adjustment value t hat shows in the same dire ction causes an immediate update of the threshold value. if the dire ction of the calculated adjustment value changes, there must be again four consecutive adjustment values in the same direction for another update of the thres hold value. additionally there is an activation level implemented, allowing the thre shold to be adjusted only if a certain amount (normally bigger than 1lsb) of adjustment is calcul ated. the threshold correction per cycle is limited to 1 lsb. the purpose of this strategy is to avoid larger offset deviations due to singular events. also irregular ities of the target wheel are cancelled out, since the minimum and maximum values ar e derived over at least one full revolution of the wheel. the output switching is done at the threshold le vel without visible hyst eresis in order to achieve maximum accuracy. nevertheless t he chip has some internal protection mechanisms in order to avoid multiple switching due to noise. changing the mode: every time after power up the chip is rese t into the initial mode. subsequent modes (precalibrated, calibrated) are entered consequently as described before. in addition, two plausibility checks are implemented in or der to enable some self-recovery strategy in case of unexpected events. first, there is a watchdog, which checks for s witching of the sensor at a certain lower speed limit. if for 12 seconds there is no switchi ng at the output, the chip is reset into the initial mode. second, the ic checks if there is signal activity seen by the digital logic and if there is no outputswitching at the same time. if the digita l circuitry expects that there should have been 4 switching events and actually no switch ing has occurred at the output, the ic is reset into the initial mode. reset: there are several conditions, which can lead to a reset condition. for the ic behaviour we have to distinguish between a ?output hol d mode?, a ?long reset?, a ?short reset? and a ?software reset?. output hold mode: this operating mode means that the output is held in the actual state and there is no reset on the digital part performed. this st ate will be released after the ic reaches his normal operation condition again and goes back into the operating mode he was before. the following conditions lead to the output hold mode: ? a drop in the supply voltage to a value less than 2.4v but higher than 2.0v for a time not longer than 1s .. 2s.
page 6 of 29 long reset: this reset means a total reset of the analogue as well as for the digital part of the ic. the output is forced to its default state (?high?). this condition remains for less than 1ms. after this time the ic is assumed to run in a stable conditio n and enters the initial mode where the output repres ents the state of the tar get wheel (prom value). the following conditions lead to a long reset: ? power-on condition. ? low supply voltage: drop of the supply volt age to values less than 2.4v for a time longer than 1s .. 2s or drop of the supply voltage to values less than 2.0v. short reset: this reset means a reset of the digital circ uitry. the output memorizes the state he had before the reset. this condition remains for approx. 1s. after that time the chip is brought into the initial mode ( output stays ?high? for approx. 200s for an untrimmed ic). then the output is released again and represents t he state of the target wheel (prom value). the following conditions lead to a short reset: ? watchdog overflow: if there is no switchin g at the output for more than 12 seconds. ? if there are four min- or max-events found without a swit ching event at the output software reset: this reset can be performed in the testmode through the serial-interface. the ic output is then used as data output fo r the serial interface. the following condition lead to a software reset: ? there is a reset applied through the serial interface table 1 shows an overview over the behaviour of the output under certain conditions. unprogrammed programmed noninverted inverted noninverted inverted output hold mode q n-1 - q n-1 q n-1 long reset high - high high short reset high - normal tpo inverted tpo initial mode high (self calibration) - normal tpo inverted tpo precalibrated mode normal - normal inverted calibrated mode normal - normal inverted q n-1 ? state of output before a reset occurs normal tpo ? ?low? if b > b tpo ; ?high? if b < b tpo inverted tpo ? ?high? if b > b tpo ; ?low? if b < b tpo normal ? ?low? if b > b threshold ; ?high? if b < b threshold inverted ? ?high? if b > b threshold ; ?low? if b < b threshold table1: output behaviour under certain conditions
page 7 of 29 hysteresis concept: there are two different hysteresis concepts implemented in the ic. the first one is called visible hysteresis , meaning that the output switching levels are changed between two distinct values (depending on the direction of the magnetic field during a switching event), whenever a cert ain amount of the magnetic field has been passing through after the last switching event. the visible hysteresis is used in the precalibrated mode of unprogrammed sens ors. see fig.1 for more details. the second form of hysteresis is called hidden hysteresis . this means, that one cannot observe a hysteresis from outside. if the value of the switchin g level does not change, the output always switches at the same level. but inside the ic there are two distinct levels close above and below the switching leve l, which are used to arm the output. in other words if the value of t he magnetic field crosses the lowe r of this hysteresis levels, then the output will be able to switch if the fi eld crosses the switching level. after this switching event the output will be disabled until the value of the magnetic field crosses one of the two hysteresis levels . if it crosses the upper hysteresis level, then the output will be armed again and can switch if the magnetic field crosse s the switching level. on the other hand, if the magnetic field does not reach the upp er hysteresis level, but the lower hysteresis level will be crossed agai n after a switching event, then the output is allowed to switch, so that no tooth will be lost. but please notice that this causes an additional phase error. the hidden hysteresis is used for programmed sensors in precalibrated and calibrated mode. for more details see fig.2
page 8 of 29 t b b b off b on b tpo b hys t q fig. 1: visible hysteresis valid for unprogrammed ic during precalibrated mode
page 9 of 29 t b b b off b on b cal b hys /2 t q fig. 2 hidden hysteresis valid for programmed ic
page 10 of 29 block diagram: the block diagram is shown in fig.3. the ic consists of a spinning hall probe (monocell in the centre of the chip) with a chopped prea mplifier. next there is a summing node for threshold level adjustment. the threshold switching is actually done in the main comparator at a signal level of ?0?. this means, that the w hole signal is shifted by this summing node in that way, that the desired switching level oc curs at zero. this adjusted signal is fed into an a/d-conver ter. the converter feeds a digital calibration logic. this logic monitors the digitised signal by look ing for minimum and ma ximum values and also calculates correction values for threshold adju stment. the static swit ching level is simply done by fetching a digital value out of a prom. the dynamic switching level is done by calculating a weighted averag e of min and max value. fo r example, a factor of approximately 71% can be achiev ed by doubling the weight of the max value. generally speaking, a threshold level of b cal = b min + (b max ? b min ) * k 0 can be achieved by multiplying max with the switching level k 0 and min with (1-k 0 ). serial interface: the serial interface is used to program the chip. at the same time it can be used to provide special settings and to read out seve ral internal registers status bits. the interface description consists of a physical layer and a logical layer. the physical layer describes format, timing and voltage information, whereas the logical layer describes the available commands and the meaning of bits, words and addresses. physical interface layer : the data transmission is done over the vs-pi n, which generates input information and clock timing, and the out-pin q, which deliver s the output data. generally the interface function is disabled; this means, that in normal operation including normal supply distortion the interface is not active and ther efore the chip operates in its normal way. a special initialisation sequence mu st be performed to enter the interface mode that is also referred to as ?testmode?. there are two po ssible ways to achieve the testmode. they are called openpoweron and opensyncvdd. for already programmed devices this initialisation procedures to testmode are not possible. the ic is still in test mode after programming the ic. it is possible to read out the programmed values as long as you do not leave the test mode. openpoweron: for a short time after power on or reset the chip monitors the output signal. the internal logic brings the output into a high impedance st ate, which will be a logical ?high? caused by the exte rnal pull-up resistor . if now the chip s ees a logical ?low? (for at least 1ms), which is an output vo ltage lower than 0.3v, the chip enters the testmode. data transmission: serial transmission is done in words (lsb first) . a logical ?1? is represented by a long (2/3 of one period) ?h igh? voltage level (higher than 5v) on the supply followed by a short (1/3 of one peri od) ?low? voltage level (lower than 5v), whereas a logical ?0? is represented by a shor t ?high? level on the supply followed by a long ?low? level. at the same time this high/ low voltage combination, which forms in fact a bit, acts as a serial interface clock whic h clocks out logical high / low values on the output. due to the increased capacity a cl ocking period of 200s is recommended (standard value for 4.7nf capacitor: 100s).
page 11 of 29 see fig.5 for a more detailed timing diagram. end of word is indicated by a long (we recommend longer than 200s, first 30s should be higher than 5v and the rest lower than 5v) ?low? supply. please note, that fo r communicating 13 bits of data 14 vs-pulses are necessary. if more than 14 input bits are transmitted the output bits are irrelevant (transmission buffer empty) whereas the input bi ts remain valid and start overwriting the previously transmitted bits. in any case the last 14 transmitted bits are interpreted as transmitted data word (13 bits) + 1 stop bit. e nd of communication is signalled by a long ?high? voltage level. a new communication has to be set up by a new initialisation sequence. programming the prom: one possibility for programming the static thres hold value is to run the ic on a testbench (or in the car), to wait until the ic has r eached the calibrated mode and then simply to issue the copy commands, which transfers the calibrated threshold value into the prom. use the following procedure for this type of programming: 1) apply an oscillating magnetic field with a su itable offset (notice that for unfused devices this offset lies in the middle of the maximum and minimum value of the magnetic field). 2) enter the testmode with the second proc edure described in the chapter ?physical interface layer?. 3) wait until the ic has reached the calibration mode. 4) choose a k-factor and supply a programming current to the output. for details see document: ?how to program tle498x?. 5) write the two following bit-combinat ions via the serial interface: 101xxxxxk 2 k 1 k 0 i1 1011111111111 here ki indicate the 3bits of the k-fact or (k2 ? msb and k0 ? lsb) in dual-code. this means: xxxx111 is equal to k0=0.7734 and xxxx011 is equal to k0=0.5234. the bit i is the so called inverting bit, wh ich determines either the output switches inverse to the applied magnetic fi eld (i=?0?) or not (i=?1?). 6) leave the testmode by writ ing a long ?high? voltage level.
page 12 of 29 a second form of programming the static threshol d value is to bring the ic in front of a target, which delivers a static magnetic fiel d with a suitable strength and perform a power on by forcing the output to a low state for at least 1ms. this brings the chip in the testmode and he starts immediately a successi ve approximation and adjusts the value of the offset-dac to the switching leve l that corresponds to the field strength. use the following procedure for this type of programming: 1) apply a static magnetic fi eld with a suitable strength. 2) enter the testmode with the first proc edure described in the chapter ?physical interface layer?. 3) wait until the ic has made the successi ve approximation and reached the right level for the offset-dac (a t least 10 periods of the internal clock frequency after releasing the output). 4) choose a k-factor and supply a programming current to the output. for details see document: ?how to program tle498x?. 5) write the two following bit-combinat ions via the serial interface: 101xxxxxk 2 k 1 k 0 i1 1011111111111 here ki indicate the 3bits of the k-fact or (k2 ? msb and k0 ? lsb) in dual-code. this means: xxxx111 is equal to k0=0.7734 and xxxx011 is equal to k0=0.5234. the bit i is the so called inverting bit, wh ich determines either the output switches inverse to the applied magnetic fi eld (i=?0?) or not (i=?1?). 6) leave the testmode by writi ng a long ?high? voltage level. it has to be noted that the ch ip has increased power dissipa tion during programming the prom/fuses. the additional power is taken out of the output. due to the prom can not be tested during the sensor production pl ease be aware that there is natural programming yield loss. furthermore there may be an influence from the programming equipment. please contact your local technical support for more details or see document: ?how to program tle498x?. overvoltage protection: the process used for production has a break through voltage of approximately 27.5v. the chip can be brought into breakthrough without damage if the breakthrough power (current) is limited to a certain value. us ually destruction is caused by overheating the device. therefore for short pulses the breakthrough power c an be higher than for long duration stress. for example for load dump c onditions an external pr otection resistor of 200 ? is recommended in 12v-systems and 50 ? in 5v-systems.
page 13 of 29 offset dac main comp digital spinning hall probe chopper & filter + - out n-channel open drain actual switching level min max algorithm prom k-factor inv. bit b tpo analog supply digital supply hall supply overtemperature & short-circuit protection supply regulator bias for temperature & technology compensation hyst comp gnd clamping clamping & reverse voltage protection interface reset oscillator vs fig.3: blockdiagram of tle4983 enable tracking adc
page 14 of 29 fig. 4: dynamic threshold value fig. 5: serial protocol
page 15 of 29 absolute maximum ratings: symbol name min typ max unit note v s supply voltage -18 18 v -24 24 v 1h with r series >=200 ? 2 -26 26 v 5min with r series >=200 ? 1 -28 28 v 1min with r series 200 ? 1 v q output off voltage -0.3 18 v -18 24 v 1h with r load >=500 ? -18 26 v 5min with r load >=500 ? -1.0 v 1h without r load v q output on voltage 16 v current internal limited by short circuit protection (72h@t a <40c) 18 v current internal limited by short circuit protection (1h@t a <40c) 24 v current internal limited by short circuit protection (1min@t a <40c) i q continuous output current -50 50 ma t j junction temperature -40 c 155 c 5000h (not additive) 165 c 2500h (not additive) 175 c 500h (not additive) 195 c 10x1h (additive to the other life times) r thja thermal resistance junction-air 190 k/w t s storage temperature -50 150 c b magnetic field induction mt no limit note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for exten ded periods may affect device reliability. esd protection parameter symbol max unit remarks esd ? protection v esd 4 kv according to standard eia/jesd22- a114-b, human body model (hbm). 2 accumulated life time
page 16 of 29 operating range: symbol name min max unit note 3.3 18 v continuous 24 v 1h with r series >=200 ?; extended limits for parameters in characteristics v s operating supply voltage 26 v 5min with r series >=200 ?; extended limits for parameters in characteristics -40 c 155 c 5000h (not additive) 165 c 2500h (not additive) t j operating junction temperature 175 c 500h (not additive) reduced signal quality permittable (e.g. jitter) t cal trimming temperature 15 35 c v s =5/12v i q continuous output on current 0 20 ma v qmax =0.5v -0.3 18 v continuous v q continuous output off voltage -0.3 24 v 1h with r load >=500 ? f b magnetic signal switching frequency 0 5 khz measured between two rising edges of the magnetic signal t edge rise time of magnetic edge 85 s magnetic signal edge is not allowed to rise faster (otherwise tracking adc is not able to follow) b magnetic switching level range -13 91 mt b tpo true power on range -13 91 mt allowed programmable tpo- values; hysteresis not included (typ. b hys =1mt) b ac_tpo magnetic signal swing for tpo-function 6 80 mt pp b tpo =33mt b hys = 0.75mt 3 b ac_cal magnetic signal swing for calibrated mode 3 80 mt pp b over magnetic overshoot 10 % of b accal k 0 adjustment range of switching level 33.59 77.34 % of b ac_cal switching point in calibrated mode is determined by: b cal = b min + (b max ? b min ) * k 0 k 0 step size = 6.25% 3 encapsulated devices with b tpo =44mt and b hys =0.5mt show minimum value of 5mt pp
page 17 of 29 symbol name min max unit note tc btpo programmable temperature coefficient of b tpo -1200 0 ppm/k range to compensate tc magnet , typical -825ppm/k -300 300 ppm/k linear tc deviation -40c to 150c 1 ? tc btpo deviation to programmed temperature coefficient of b tpo -3.75 3.75 % at -40c and 150c see figure 6 1 450ppm/k @ -40c guaranteed by design refered to second order tc btpo compensation. furthermore this compensation comprises the adjustment to second order effect of magnet note: in the operating range the functions giv en in the functional description are fullfiled figure 6: deviation to programmed temperature coefficient of btpo
page 18 of 29 ac/dc characteristics: symbol name min typ max unit note v qsat output saturation voltage 0.25 0.5 v i q = 20ma i qleak output leakage current 0.1 10 a v q = 18v i qshort currentlimit for shortcircuit protection 30 50 80 ma t prot junction temperature limit for output protection 195 210 230 c t rise 4 output rise time 4 11 17 s v load = 4,5..24v r load = 1k ?, c load = 4,7nf included in package t fall 5 output fall time 1.4 2.4 2.4 4 3.4 5.6 s s v load = 5v; v load = 12v; r load = 1k ?, c load = 4,7nf included in package i svmin supply current @ 3.2v 6 7 ma v s = 3.2v; extended limits for parameters in characteristics i sv supply current @ 3.3v 6 7 ma v s = 3.3v; i s supply current 5.6 7.5 ma i smax supply current @ 24v 8.0 ma r series >=200 ? v sclamp clamping voltage v s -pin 24 27.5 v 1ma through clamping device v qclamp clamping voltage q-pin 24 27.5 v 1ma through clamping device v sreset analog reset voltage 2.35 2.9 v 0.56 6 1 ms t on power on time 0.75 8 ms time to achieve specified accuracy. during this time the output is locked 7 t d 9 delay time of output to magnetic edge 8 15 22 s higher magnetic slopes and overshoots reduce t d , because the signal is filtered internal. 10 ? t d temperature drift of delay time of output to magnetic edge -3.6 3.6 s not additional to t d n watch watchdog edges 4 - if n watch min or max-events have been found and there was no change at the output a reset is performed. t watch watchdog time 12 s if there is no output change during t watch a reset is performed. 4 value of capacitor: 4.7nf 10%;(excluded drift due to temperature and over lifetime); ceramic: x8r; maximum voltage: 50v 5 value of capacitor: 4.7nf 10%;(excluded drift due to temperature and over lifetime); ceramic: x8r; maximum voltage: 50v 6 trimmed ic. 7 output is in high-state. 8 untrimmed ic. 9 measured at t j = 25c; represents the influence of th e production spread (corresponds to the 3 -value). 10 measured with a sinusoidal-field magnetic-f ield with 10mtpp and a frequency of 1khz.
page 19 of 29 symbol name min typ max unit note f clk clock frequency for digital part 1.76 mhz f chopper clock frequency used by the chopper preamplifier 220 khz output jitter is not affected by the chopper frequency ? k 0 resolution of switching level adjustment 6.25 % b offset internal offset -2.2 0.35 2.2 mt typ. value corresponds 1 fsr odac full scale range of the offset-dac 104 130 162.5 mt typ. b odac_0 = -16.3mt typ. b odac_1023 = 113.8mt fsr odactyp full scale range of the offset-dac 112.7 130 152.8 mt t j =25c b tpo_res resolution of programmable threshold in tpo mode 0.13 mt ? b tpo drift of b tpo -point -2 +3.4 mt b tpo =33mt 11 ? b ac_cal accuracy of threshold in calibration mode -2 2 % percentage of b ac ; b ac =10mt pp sinusoidal signal 12 ; systematic deviation due to hysteresis in the filter algorithm of 1.5% at b ac =10mt pp not included; b neff effective noise value of the magnetic switching points 33 t t j = 25c; the magnetic noise is normal distributed, nearly independent to frequency and without sampling noise or digital noise effects. the typical value represents the rms-value here and corresponds therefore to 1 probability of normal distribution. consequently a 3 value corresponds to 0.3% probability of appearance. 55 120 t the typical value corresponds to the rms-value at t j = 175c . the max value corresponds to the rms-values in the full temperature range and includes technological spreads. note: the listed ac/dc and magnetic char acteristics are ensured over the operating range of the integrated circuit. typical char acteristics specify mean values expected over the production spread. if not other spec ified, typical characteristics apply at t j = 25 c and v s = 12 v. 11 this value shows the deviation from the programmed b tpo value and its temperature coefficient. included are the package-effect, the deviation from the adjusted temperat ure coefficient of the b tpo point (resolution of the temper ature coefficient and spread of the technologie) and the drift of the offset (over temperature and lifetime). not included is the hysteresis in the initial mode. included are the package-ef fect, the deviation from the adjusted temperature coefficient of the b tpo point (resolution of the temperature coefficient a nd spread of the technologie) and the drift of the offset (over temperature and lifetime). not in cluded is the hysteresis in the initial mode. 12 bigger amplitudes of signal l ead to smaller values of ? b ac_cal .
page 20 of 29 application circuit figure 7 application circuits tle4983c for example: r l =1,2k ? r s =120 ? 3 1 2 1 3 2 for example: r p 200 ? @ vs=12v r p 50 ? @ vs=5v r l =1,2k ?
page 21 of 29 electro magnetic compatibility - (values depend on r series ) additional information: characterisation of electro magnetic compatibility ar e carried out on sample base of one qualification lot. not all specification parameters have been monitored during emc exposure. only key parameters e.g. switching current and duty cycle have been monitored. ref. iso 7637-1; see test circuit of figure 8; ? b pp = 10mt (ideal sinusoidal signal); v s =13.5v 0.5v, f b = 1000hz; t= 25c; r series 200 ?; parameter symbol level/typ status testpulse 1 testpulse 2 testpulse 3a testpulse 3b testpulse 4 v emc iv / -100v iv / 100v iv / -150v iv / 100v iv / -7v c a 13 a a a ref. iso 7637-2; 2 nd edition 06/2004 see test circuit of figure 8; ? b pp = 2mt (amplitude sinus signal); v s =13.5v 0.5v, f b = 1000hz; t= 25c; r series 200 ?; parameter symbol level/typ status testpulse 2a testpulse 5a testpulse 5b v emc iv / 40v iv / 86.5v iv / 86.5v a c a 14 note: test criteria for status a: no missi ng pulse no additional pulse on the ic output signal plus duty cycle and jitter are in the specification limits. test criteria for status b: no missing pulse no additional pulse on the ic output signal. (output signal ?off? means switching to the voltage of the pu ll-up resistor). test criteria for status c: one or more parameter can be out of specification during the exposure but returns automatically to normal operation after exposure is removed. test criteria for status e: destroyed. 13 valid during vs is applied afterwards status c, current consumption may be out of spec during testpulse 14 suppressed us*=35v
page 22 of 29 ref. iso 7637-3; tp 1 and tp 2 ref. din 40839-3; see test circuit of figure 8; ? b pp = 10mt (ideal sinusoidal signal); v s =13.5v 0.5v, f b = 1000hz; t= 25c; r series 200 ? ; parameter symbol level/typ status testpulse 1 testpulse 2 testpulse 3a testpulse 3b v emc iv / -30v iv / 30v iv / -60v iv / 40v a a a a ref. iso 11452-3; see test circuit of figure 8; measured in tem-cell; ? b pp = 4mt (ideal sinusoidal signal); v s =13.5v 0,5v, f b = 200hz; t= 25c; r series 200 ? ; parameter symbol level/max remarks emc field strength e tem-cell iv / 200v/m am=80%, f=1khz; note: stresses above those listed here ma y cause permanent damage to the device. exposure to absolute maximum rating condi tions for extended periods may affect device reliability. test conditi on for the trigger window: f b-field =200hz, b pp =4mt, vertical limits are 200mv and horizontal limits are 200s. figure 8: testcirc uit for emc-tests 1k ? 50pf v emc r series v s gnd q c load r load 5v 200 ? c int-package c int-package 47 nf 4.7 nf
page 23 of 29 package dimensions pg-sso 3-91 ( p lastic g reen s ingle s mall o utline)
page 24 of 29 position of the hall element
page 25 of 29 appendix: calculation of mechanical errors: ? ?? ?? magnetic signal output signal figure 9: systematic error ? and stochastic error ?? systematic phase error ? the systematic error comes in because of the delay-time between the threshold point and the time when the output is switching. it can be calculated as follows: d t n ? ? = 60 360 ? ? ... systematic phase error in n ... speed of the camshaft-wheel in min -1 t d ... delay time (see specification) in sec
page 26 of 29 noise 1 bneff_typ bn_max 3 b ? ? ? ? b phase-jitter figure 10: phase-jitter stochastic phase error ?? the stochastic phase error includes the error due to the variation of the delay time with temperature and the error caused by the resolution of the thres hold. it can be calculated in the following way: d d t n ? ? ? = ? 60 360 ? cal ac cal b b _ ? ? ? ? = ? ? ? ?? d ... stochastic phase error due to the variation of the delay time over temperature in ?? cal ... stochastic phase error due to t he resolution of the th reshold value in n ... speed of the camshaft wheel in min -1 b ? ? ? ... inverse of the magnetic slope of the edge in / t ? t d ... variation of dela y time over temperature in sec ? b ac_cal ... accuracy of the threshold in t jitter (repeatability) the phase jitter is normally caused by the analogue system noise. if there is an update of 1bit of the offset-dac due to the algorithm, what could happen after a period of 16 teeth, then an additional step in the phase occurs (see description of the algorithm). this is not included in the following calculations. the noise is transformed through the slope of the magnetic edge into a phase error. the phase jitter is determined by the two formulas: () typ neff typ jitter b b _ _ ? ? ? = ? ? () max _ max _ n jitter b b ? ? ? = ? ?
page 27 of 29 ? jitter_typ ... typical phase jitter at tj=25c in (1sigma) ? jitter_max ... maximum phase jitter at tj=175c in (3sigma) b ? ? ? ... inverse of the magnetic slope of the edge in / t b neff_typ ... typical value of b neff in t (1 -value at tj=25c) b n_max ... maximum value of b n in t (3 -value at tj=175c) example: assumption: n = 3000 min -1 t d = 14 s ? t d = 3 s ? ? ? b = 1 mt/ ? b ac_cal = 0.2 mt (=2% of 10mt swing) b neff_typ = 33 t (1 -value at t=25c) b n_max = 360 t (3 -value at t=170c) calculation: ? = 0.252 ... systematic phase error ?? d = 0.054 ... stochastic phase error due to delay time variation ?? cal = 0.2 ... stochastic phase error due to accuracy of the threshold ? jitter_typ = 0.033 ... typical phase jitter (1 -value at tj=25c) ? jitter_max = 0.21 ... maximum phase jitter (3 -value at tj=175c)
page 28 of 29 appendix a: marking & data matrix code information: product is rohs (restriction of hadzardous substances) compliant when marked with letter ?g? in front or afte r the date code marking. as mentioned in information note n 136/03 a data matrix code with 8x18 fields according to the ecc200 standard may be used for tle4983c. furthermore the marking technique on the front side of t he device may be changed from a mask to a writing laser equipment. the in formation content (date code and device type) will hereby not be changed. please refer to you key account team or r egional sales responsible if you need further information example for data matrix code (rear side of sensor): comparison between mask writing vs. new laser writing (tle 4941): mask lasering writing lasering
page 29 of 29 revision history: version 1.1 previous version: 1.1 23 change: new package outline figure 25 old package outline figure erased infineon technologies ag ? infineon technologies ai sc all rights reserved. http://www.infineon.com/products/sensors we listen to your comments any information within this document that you f eel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: sensors@infineon.com

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